Increasing pin counts, as well as faster circuit speeds, have compounded the need for reliable ESD protection in integrated circuits (ICs). Input/output signals to a complimentary metal oxide semiconductor (CMOS) circuit are typically fed to input/output pads which are connected to the gates of metal oxide semiconductor (MOS) transistors. If a high static discharge voltage is accidentally applied to any of the input/output pins of an IC, the input/output transistor's gate insulator and the contacts between the pad and the underlying active area are vulnerable to damage if adequate ESD protection is not present. Therefore, all pins of MOS ICs must be ESD protected to prevent any harmful static discharge voltages from damaging the IC.
Four main types of ESD protection circuits have been implemented in IC design which are intended to provide a current path to ground to absorb the high static discharge voltage. These four main ESD protection circuits include: 1) diode breakdown, 2) node-to-node punchthrough, 3) gate-field-induced breakdown, and 4) parasitic pnpn diode latchup.
Operation and construction of each of the four main types of ESD protection circuits have been described in various publications, such as the textbook "SILICON PROCESSING FOR THE VLSI ERA--VOLUME II, 1990, pp. 442-446 and therefore are not described further herein.
Also an input ESD protection circuit is described in two articles: the first article is entitled "A PROCESS-TOLERANT INPUT PROTECTION CIRCUIT FOR ADVANCED CMOS PROCESSES", Roundtree et. al., 1988 EOS/ESD SYMPOSIUM PROCEEDINGS, pp. 201-205, and the second article is entitled "INPUT PROTECTION DESIGN FOR OVERALL CHIP RELIABILITY", C. Duvvury et. al., 1989 EOS/ESD SYMPOSIUM PROCEEDINGS, pp. 190-197.
The first article describes a process-tolerant input protection circuit for advanced CMOS processes based on a lateral silicon controlled rectifier (LSCR). This article shows that LSCR devices when applied in many applications have failure thresholds of greater than +/-6000V. FIG. 2, of this article shows the LSCR device which is a variation of the pnpn-diode ESD protection circuit. The second article does a study on the LSCR circuit.
Though the LSCR circuit mentioned above provides reasonable ESD protection, even greater protection is desired. The input ESD protection circuit of the present invention provides greater than +/-7000V ESD protection response due to its unique circuit fabrication layout.
All articles and publications cited herein are hereby incorporated by reference.